1. Field of the Invention
Example embodiments of the present invention relate to generally to a semiconductor memory device and method thereof.
2. Description of the Related Art
A manufacturing process for a conventional semiconductor memory device, such as a dynamic random access memory (DRAM), may include several processes, such as designing, processing, chip testing and package testing. In the chip testing process, the semiconductor memory device may be tested. For example, during a parallel bit test (PBT) process, data may be written to a cell and the written data may be read to determine if the cell is defective based on a comparison between the read data and the written data. In the PBT process, data on a data line in the read operation may be merged for testing. The testing may typically be performed in units of one cell or one bit line to determine whether the data on that particular bit line is normal. The testing phase of the manufacturing process is typically a time-consuming and costly process. To reduce costs associated with the testing phase, data in a plurality of cells and/or on a plurality of bit lines may be logically combined using comparators and the resulting signal may be used for testing (e.g., to determine relatively quickly whether any of the plurality of cells/bit lines includes an error).
For example, if data is output in units of 4 bits, 4-bit data signals may be input to the comparator. The comparator may compare the input signals to determine whether each input signal is the same. Thus, the same data may be written to each cell to determine whether one or more of the cells are defective based on an output signal of the comparator.
In the conventional PBT process, the output signals of the comparators may each be output via a data input/output pad DQ for each comparator. Accordingly, the output signals of the comparators may be output to respective data input/output pads DQ via data lines. If a given cell is determined to be defective, a block including the defective cell may be replaced or “repaired” with a redundancy cell block. That is, the block including the defective cell may be replaced with the redundancy cell block. The redundancy cell block may hold address information of the block including the defective cell as its fuse is cut.
In the conventional PBT process, the output signals of the comparators may be used for testing the output signals one by one (e.g., because each comparator outputs its results on a separate data input/output pad DQ). The conventional PBT process may be a relatively time consuming and expensive process.